[PATCH 1/2] powerpc/powernv/npu: Move tlb flush before launching ATSD

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[PATCH 1/2] powerpc/powernv/npu: Move tlb flush before launching ATSD

Alistair Popple
The nest mmu tlb flush needs to happen before the GPU translation shootdown
is launched to avoid the GPU refilling its tlb with stale nmmu translations
prior to the nmmu flush completing.

Signed-off-by: Alistair Popple <[hidden email]>
Cc: [hidden email]
---
 arch/powerpc/platforms/powernv/npu-dma.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
index b5d960d..3d4f879 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -546,6 +546,12 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,
  unsigned long pid = npu_context->mm->context.id;
 
  /*
+ * Unfortunately the nest mmu does not support flushing specific
+ * addresses so we have to flush the whole mm.
+ */
+ flush_tlb_mm(npu_context->mm);
+
+ /*
  * Loop over all the NPUs this process is active on and launch
  * an invalidate.
  */
@@ -576,12 +582,6 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,
  }
  }
 
- /*
- * Unfortunately the nest mmu does not support flushing specific
- * addresses so we have to flush the whole mm.
- */
- flush_tlb_mm(npu_context->mm);
-
  mmio_invalidate_wait(mmio_atsd_reg, flush);
  if (flush)
  /* Wait for the flush to complete */
--
2.1.4

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[PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb

Alistair Popple
The nest mmu required an explicit flush as a tlbi would not flush it in the
same way as the core. However an alternate firmware fix exists which should
eliminate the need for this flush, so instead add a device-tree property
(ibm,nmmu-flush) on the NVLink2 PHB to enable it only if required.

Signed-off-by: Alistair Popple <[hidden email]>
---

Michael,

This patch depends on http://patchwork.ozlabs.org/patch/796775/ - [v3,1/3]
powerpc/mm: Add marker for contexts requiring global TLB invalidations.

- Alistair

 arch/powerpc/platforms/powernv/npu-dma.c | 27 +++++++++++++++++++++------
 arch/powerpc/platforms/powernv/pci.h     |  3 +++
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
index 3d4f879..ac07800 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -544,12 +544,7 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,
  struct pci_dev *npdev;
  struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];
  unsigned long pid = npu_context->mm->context.id;
-
- /*
- * Unfortunately the nest mmu does not support flushing specific
- * addresses so we have to flush the whole mm.
- */
- flush_tlb_mm(npu_context->mm);
+ bool nmmu_flushed = false;
 
  /*
  * Loop over all the NPUs this process is active on and launch
@@ -566,6 +561,17 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,
  npu = &nphb->npu;
  mmio_atsd_reg[i].npu = npu;
 
+ if (nphb->npu.nmmu_flush && !nmmu_flushed) {
+ /*
+ * Unfortunately the nest mmu does not support
+ * flushing specific addresses so we have to
+ * flush the whole mm once before shooting down
+ * the GPU translation.
+ */
+ flush_tlb_mm(npu_context->mm);
+ nmmu_flushed = true;
+ }
+
  if (va)
  mmio_atsd_reg[i].reg =
  mmio_invalidate_va(npu, address, pid,
@@ -732,6 +738,13 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
  return ERR_PTR(-ENODEV);
  npu_context->npdev[npu->index][nvlink_index] = npdev;
 
+ if (!nphb->npu.nmmu_flush)
+ /*
+ * If we're not explicitly flushing ourselves we need to mark
+ * the thread for global flushes
+ */
+ mm_context_set_global_tlbi(&mm->context);
+
  return npu_context;
 }
 EXPORT_SYMBOL(pnv_npu2_init_context);
@@ -829,6 +842,8 @@ int pnv_npu2_init(struct pnv_phb *phb)
  static int npu_index;
  uint64_t rc = 0;
 
+ phb->npu.nmmu_flush =
+ of_property_read_bool(phb->hose->dn, "ibm,nmmu-flush");
  for_each_child_of_node(phb->hose->dn, dn) {
  gpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));
  if (gpdev) {
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index f16bc40..e8e3e20 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -184,6 +184,9 @@ struct pnv_phb {
 
  /* Bitmask for MMIO register usage */
  unsigned long mmio_atsd_usage;
+
+ /* Do we need to explicitly flush the nest mmu? */
+ bool nmmu_flush;
  } npu;
 
 #ifdef CONFIG_CXL_BASE
--
2.1.4

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Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb

kbuild test robot
Hi Alistair,

[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.13-rc4 next-20170811]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Alistair-Popple/powerpc-powernv-npu-Move-tlb-flush-before-launching-ATSD/20170813-211752
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=powerpc

All errors (new ones prefixed by >>):

   arch/powerpc/platforms/powernv/npu-dma.c: In function 'pnv_npu2_init_context':
>> arch/powerpc/platforms/powernv/npu-dma.c:746:3: error: implicit declaration of function 'mm_context_set_global_tlbi' [-Werror=implicit-function-declaration]
      mm_context_set_global_tlbi(&mm->context);
      ^~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: all warnings being treated as errors

vim +/mm_context_set_global_tlbi +746 arch/powerpc/platforms/powernv/npu-dma.c

   652
   653 /*
   654 * Call into OPAL to setup the nmmu context for the current task in
   655 * the NPU. This must be called to setup the context tables before the
   656 * GPU issues ATRs. pdev should be a pointed to PCIe GPU device.
   657 *
   658 * A release callback should be registered to allow a device driver to
   659 * be notified that it should not launch any new translation requests
   660 * as the final TLB invalidate is about to occur.
   661 *
   662 * Returns an error if there no contexts are currently available or a
   663 * npu_context which should be passed to pnv_npu2_handle_fault().
   664 *
   665 * mmap_sem must be held in write mode.
   666 */
   667 struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
   668 unsigned long flags,
   669 struct npu_context *(*cb)(struct npu_context *, void *),
   670 void *priv)
   671 {
   672 int rc;
   673 u32 nvlink_index;
   674 struct device_node *nvlink_dn;
   675 struct mm_struct *mm = current->mm;
   676 struct pnv_phb *nphb;
   677 struct npu *npu;
   678 struct npu_context *npu_context;
   679
   680 /*
   681 * At present we don't support GPUs connected to multiple NPUs and I'm
   682 * not sure the hardware does either.
   683 */
   684 struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
   685
   686 if (!firmware_has_feature(FW_FEATURE_OPAL))
   687 return ERR_PTR(-ENODEV);
   688
   689 if (!npdev)
   690 /* No nvlink associated with this GPU device */
   691 return ERR_PTR(-ENODEV);
   692
   693 if (!mm || mm->context.id == 0) {
   694 /*
   695 * Kernel thread contexts are not supported and context id 0 is
   696 * reserved on the GPU.
   697 */
   698 return ERR_PTR(-EINVAL);
   699 }
   700
   701 nphb = pci_bus_to_host(npdev->bus)->private_data;
   702 npu = &nphb->npu;
   703
   704 /*
   705 * Setup the NPU context table for a particular GPU. These need to be
   706 * per-GPU as we need the tables to filter ATSDs when there are no
   707 * active contexts on a particular GPU.
   708 */
   709 rc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,
   710 PCI_DEVID(gpdev->bus->number, gpdev->devfn));
   711 if (rc < 0)
   712 return ERR_PTR(-ENOSPC);
   713
   714 /*
   715 * We store the npu pci device so we can more easily get at the
   716 * associated npus.
   717 */
   718 npu_context = mm->context.npu_context;
   719 if (!npu_context) {
   720 npu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);
   721 if (!npu_context)
   722 return ERR_PTR(-ENOMEM);
   723
   724 mm->context.npu_context = npu_context;
   725 npu_context->mm = mm;
   726 npu_context->mn.ops = &nv_nmmu_notifier_ops;
   727 __mmu_notifier_register(&npu_context->mn, mm);
   728 kref_init(&npu_context->kref);
   729 } else {
   730 kref_get(&npu_context->kref);
   731 }
   732
   733 npu_context->release_cb = cb;
   734 npu_context->priv = priv;
   735 nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
   736 if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
   737 &nvlink_index)))
   738 return ERR_PTR(-ENODEV);
   739 npu_context->npdev[npu->index][nvlink_index] = npdev;
   740
   741 if (!nphb->npu.nmmu_flush)
   742 /*
   743 * If we're not explicitly flushing ourselves we need to mark
   744 * the thread for global flushes
   745 */
 > 746 mm_context_set_global_tlbi(&mm->context);
   747
   748 return npu_context;
   749 }
   750 EXPORT_SYMBOL(pnv_npu2_init_context);
   751

---
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