[PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

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[PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

Thomas Breitung
The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
before a new value can be or-ed in.

Signed-off-by: Thomas Breitung <[hidden email]>
Signed-off-by: Wolfgang Ocker <[hidden email]>
---
 drivers/dma/fsldma.c | 5 ++++-
 drivers/dma/fsldma.h | 4 ++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 51c75bf2b9b6..3b8b752ede2d 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -269,6 +269,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
  case 2:
  case 4:
  case 8:
+ mode &= ~FSL_DMA_MR_SAHTS_MASK;
  mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
  break;
  }
@@ -301,6 +302,7 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
  case 2:
  case 4:
  case 8:
+ mode &= ~FSL_DMA_MR_DAHTS_MASK;
  mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
  break;
  }
@@ -327,7 +329,8 @@ static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
  BUG_ON(size > 1024);
 
  mode = get_mr(chan);
- mode |= (__ilog2(size) << 24) & 0x0f000000;
+ mode &= ~FSL_DMA_MR_BWC_MASK;
+ mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK;
 
  set_mr(chan, mode);
 }
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 31bffccdcc75..4787d485dd76 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -36,6 +36,10 @@
 #define FSL_DMA_MR_DAHE 0x00002000
 #define FSL_DMA_MR_SAHE 0x00001000
 
+#define FSL_DMA_MR_SAHTS_MASK 0x0000C000
+#define FSL_DMA_MR_DAHTS_MASK 0x00030000
+#define FSL_DMA_MR_BWC_MASK 0x0f000000
+
 /*
  * Bandwidth/pause control determines how many bytes a given
  * channel is allowed to transfer before the DMA engine pauses
--
2.13.0

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Re: [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

Vinod Koul
On Mon, Jun 19, 2017 at 04:40:04PM +0200, Thomas Breitung wrote:
> The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
> before a new value can be or-ed in.

Applied, thanks

--
~Vinod